1. Field of the Invention
The present invention relates to a booster device for boosting an internal potential (e.g., V.sub.pp level) in a semiconductor memory device.
2. Description of the Related Art
FIG. 2 shows a conventional example of a booster device for boosting a V.sub.pp level. The structure and operation of the booster device can be described as follows.
A conventional booster device includes an inverter I16, transistors Q13 and Q14, and a capacitor C15. A terminal 12 is connected to an input of the inverter I16. An output of the inverter I16 is connected to gates of the transistors Q13 and Q14. The output of the inverter I16 and the gates of the transistors Q13 and Q14 are connected together at a node 17. A power source level V.sub.pp is supplied to the inverter I16. A power source level V.sub.cc is supplied to a drain of the transistor Q13. A source of the transistor Q13 is connected to a drain of the transistor Q14 and one of electrodes of the capacitor C15. The source of the transistor Q13 the drain of the transistor Q14 and the one of the electrodes of the capacitor C15 are connected at a node 18. Another electrode of the capacitor C15 is connected to a terminal 11. A power source level V'.sub.pp to a semiconductor memory device 17' is provided at a source of the transistor Q14.
In the conventional booster device of FIG. 2, when the terminals 11 and 12 are grounded, for example, by being connected to V.sub.GND via an external circuit including switches SW1 and SW2, a level of an input signal to the inverter I16 is a logic LOW. When the level of the input signal to the inverter I16 is LOW, the level of an output signal from the inverter I16 is HIGH. When the level of the output signal from the inverter I16 is HIGH, the transistor Q13 is ON and the transistor Q14 is OFF. When the transistor Q13 is ON, the voltage across the capacitor C15 is increased to the level of V.sub.cc. The power source level V.sub.pp, serving as the supply voltage to the inverter I16, is supplied as the logic HIGH level to the gates of the transistors Q13 and Q14 via the inverter I16 output and the node 17.
Then, the terminals 11 and 12 are connected to a logic HIGH level via a power supply PS and switches SW1, SW2, for example, whereby the level of the output signal from the inverter I16 becomes a logic LOW level. When the level of the output signal from the inverter I16 is LOW, the transistor Q13 is OFF and the transistor Q14 is ON. When the transistor Q14 is ON, a charge of the capacitor C15 is discharged as the power source level V'.sub.pp to the semiconductor memory device via the transistor Q14.
In the above-described conventional booster device, the electrical potential at the node 17 is decreased in the event that the V.sub.pp level at the time when power to the booster device is turned on does not reach a sufficiently high level. Thus, there is a problem that the transistor Q13 will not be turned on completely. Since the transistor Q13 is not turned on completely, the capacitor C15 is not charged completely, and in particular, the V'.sub.pp level is resultantly a lower power source voltage.
In view of the aforementioned shortcoming associated with a conventional booster device, there exists a strong need in the art for a booster circuit which ensures that a transistor for charging a capacitor is turned on fully, irrespective of the V.sub.pp level.